1. Field of the Invention
The present invention relates to an IC card connected to an external device for executing data processing and a semiconductor integrated circuit used for the same.
2. Description of the Related Art
The construction of a conventional IC card 20 is shown in FIG. 6. A ROM 24, an EEPROM 25 and a RAM 26 are connected via a system bus 22 to a CPU 21 for executing calculations and controlling operations required for data processing. The ROM 24 writes a program for executing various functions used by a card user. The EEPROM 25 writes individual information, or the like, of a card user. The RAM 26 temporarily stores the data required for data processing. An input/output (I/O) circuit 27 for data I/O communication with an external unit is also connected to the system bus 22. The conventional IC card also includes terminals such as a positive-power supply input terminal P1, a negative-power supply ground terminal P2, a reset terminal P3 for receiving a reset signal to initialize the CPU 21, a clock terminal P4 for receiving an external clock signal Xin, and an I/O terminal P5 for data I/O processing.
A block diagram of the EEPROM 25 is shown in FIG. 7. A memory array 1 has a plurality of word lines 1a from an X decoder 2 to a plurality of VppSWs switches 7 and a plurality of bit lines 1b from a Y gate 3 to a plurality of VppSWs switches 8. Each of memory cells 1c is connected at the intersection of the word line 1a and the bit line 1b.
The control circuit 11 is a sequential circuit having four states such as READY, LATCH, ERASE and WRITE using an internal clock signal .phi..sub.1 of a machine cycle of the CPU 21 as a clock. The READY state is not a writing state of the control circuit 11. The control circuit 11 outputs a latch signal, an erase signal and a write signal in the LATCH, ERASE and WRITE states, respectively. Upon detection that is being written by the CPU 21 into the EEPROM 25, the control circuit 11 goes into the LATCH state and sequentially stores the data supplied from the CPU 21 to a column latch 9. The control circuit 11 also goes into the ERASE state in response to a write instruction from the CPU 21, and then, to the WRITE state, and is finally completed.
In accordance with the internal clock signal .phi..sub.1 generated by the CPU 21, the timer 12 measures the time required from latching of data to the next following data and the time required from latching the data to inputting a write instruction. When the measured time exceeds a predetermined time out period, the control circuit 11 determines that an abnormal condition exists, thus nullifying and not completing the previous operation. When the control circuit 11 generates an erase signal and a write signal, it also outputs a Vpp generating signal to the charge pump 10. When the Vpp generating signal is input into the charge pump 10 from the control circuit 11, the charge pump 10 raises the Vcc power supply voltage by an external clock signal Xin which is input via the clock terminal P4 and generates the high voltage Vpp for writing and supplies it to the VppSWs switches 7 and 8.
According to an address signal stored in an address latch 13, the X decoder 2 and the Y decoder 4 selects the word line 1a and the Y gate 3, respectively. A signal from the CPU 21 is input into the selected Y gate 3 via a data bus and a driver 5. The signal from the Y gate 3 is connected to the data bus via a sense amplifier 6.
The VppSW switches 7 supply the high voltage Vpp for the writing supplied from the charge pump 10 to the word line 1a selected by the X decoder 2. The VppSW switches 8 supply the high voltage Vpp to the respective bit lines 1b on the basis of information stored in the column latch 9. The writing data from the driver 5 is stored in the column latch 9 by way of the selected bit line 1b and VppSW switch 8.
In general, since an EEPROM requires a long write time, a plurality of data items to be written are stored in the column latch 9 and written in the memory cells 1c on the selected word lines 1a, simultaneously, thereby effectively reducing the write time.
A gate 15 generates a signal for selecting an EEPROM in accordance with the address signal from the CPU 21. A rise control circuit 14 for raising the high voltage Vpp slowly operates in accordance with the internal clock signal .phi..sub.1 from the CPU 21 and outputs a rise control signal to the charge pump 10.
However, the conventional EEPROM has the following problems. As stated above, the external clock signal Xin which is input via the clock terminal P4 for the operation of the CPU 21 and supplied to the CPU 21 is also used as a clock of the charge pump 10 of the EEPROM 25. Hence, when the frequency of the external clock signal Xin is lowered in order to vary the operation speed of the CPU 21, the high voltage Vpp for writing generated from the charge pump 10 is also lowered, thus inhibiting correct operation.
Also, the frequency of the internal clock signal .phi..sub.1 generated in the CPU 21 is changed as the frequency of the external clock signal Xin is changed. Further, the write time determined by the timer 12 operating according to the internal clock signal .phi..sub.1 is inevitably changed, thus making it difficult to ensure the optimal write time for guaranteeing the reliability of the memory cell 1c and for sufficient writing.